Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

By Design With Calibre
5 MIN READ
Pattern Matching in Design Verification

Pattern Matching in Design Verification

June 1, 2016

By Michael White, Mentor Graphics Automated pattern matching can solve a wide range of design verification issues. Are you in…

By Design With Calibre
7 MIN READ
Efficient Parasitic Extraction Techniques for Full-Chip Verification

Efficient Parasitic Extraction Techniques for Full-Chip Verification

May 26, 2016

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…

By Design With Calibre
6 MIN READ
How Do I ECO a Multi-Patterned Design?

How Do I ECO a Multi-Patterned Design?

May 11, 2016

By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multi­patterned designs can be a nightmare, unless you plan…

By Design With Calibre
7 MIN READ
Colorless vs. Colored Double-Patterning Design Flows

Colorless vs. Colored Double-Patterning Design Flows

April 18, 2016

By David Abercrombie, Mentor Graphics How do you know which double patterning flow to use?

By Design With Calibre
< 1 MIN READ
Collaborative SoC Verification

Collaborative SoC Verification

April 11, 2016

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…

By Design With Calibre
4 MIN READ
Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

April 5, 2016

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan, Mentor Graphics Optimizing power usage for mobile devices at advanced…

By Design With Calibre
8 MIN READ
When and How Should I Color My DP Layout?

When and How Should I Color My DP Layout?

March 29, 2016

By David Abercrombie, Mentor Graphics Automated DP coloring solutions minimize DP errors. But when is the best time and how…

By Design With Calibre
< 1 MIN READ
Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

March 15, 2016

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques

By Design With Calibre
7 MIN READ