Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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Calibre and the Semiconductor Ecosystem

April 12, 2021

The Semiconductor Ecosystem- It is the definition of “High Tech”, but it isn’t just about technology, there are two other…

By Design With Calibre
< 1 MIN READ

Collaboration and innovation thrive on diversity

April 5, 2021

Back in November 2019, just a few short months before we all began an enforced year of isolation and separation,…

By Design With Calibre
2 MIN READ

What is critical area analysis and why should I care?

April 1, 2021

By Simon Favre What makes money in the semiconductor industry? A killer IC design? Something so innovative that it blows…

By Design With Calibre
3 MIN READ

Adaptive Patterning: Moving with the times (and technologies)

March 24, 2021

By John Ferguson and Kevin Rinebold Deca Technologies’ Adaptive Patterning technology and their newly-announced adaptive patterning design kit (APDK) have…

By Design With Calibre
2 MIN READ

Building a strong reliability foundation with Calibre PERC

March 9, 2021

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…

By Design With Calibre
3 MIN READ
Machine learning-enabled closed loop DFM

SPIE-ing at a distance…

March 3, 2021

The SPIE Advanced Lithography Digital Forum took place Feb 22-26, and of course, Siemens EDA was there! We wouldn’t miss…

By Design With Calibre
< 1 MIN READ

Early circuit verification can get you to tapeout faster…here’s how

February 4, 2021

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing…

By Design With Calibre
2 MIN READ

Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…

By Design With Calibre
2 MIN READ

Stochasticity of the input current is an important factor in accurate EM assessment for on-chip power delivery networks

January 18, 2021

At every conference, there is always that anticipatory moment just before the coveted “Best Paper” awards are announced. After all,…

By Design With Calibre
2 MIN READ