No to Know VIP – Part 3

No to Know VIP – Part 3

Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT…

Ready for a Verification Extravaganza in the Land of Verification Engineers?

Ready for a Verification Extravaganza in the Land of Verification Engineers?

I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines…

Part 11: The 2014 Wilson Research Group Functional Verification Study

Part 11: The 2014 Wilson Research Group Functional Verification Study

ASIC/IC Power Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group…

Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…

An Agile Evolution in SoC Verification Panel @ DAC

An Agile Evolution in SoC Verification Panel @ DAC

This year we are trying something new at the Verification Academy booth during next week’s 2015 Design Automation Conference.  We’ve…

Part 4: The 2014 Wilson Research Group Functional Verification Study

Part 4: The 2014 Wilson Research Group Functional Verification Study

FPGA Verification Effectiveness Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research…

Part 3: The 2014 Wilson Research Group Functional Verification Study

Part 3: The 2014 Wilson Research Group Functional Verification Study

FPGA Effort Verification Trends (Continued) This blog is a continuation of a series of blogs related to the 2014 Wilson…

ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design,…

The FPGA Verification Window Is Open

The FPGA Verification Window Is Open

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…