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DFT for AI chips draws a crowd at ITC India tutorial

At the recently concluded ITC India conference, Mentor experts presented the two highest-attended tutorials. One…

How-to implement hierarchical DFT on Arm cores

The new reference flow jointly developed by Arm and Mentor for hierarchical DFT and ATPG…

DFT architectural tips: the importance of reference flows

This video, the last in a series of three, discusses the Tessent platform capabilities and…

DFT architectural tips: use of boundary scan chain during ATPG

DFT designers often use boundary scan chains for 1149.1 or 1149.6 interconnect tests. This video…

DFT architectural tips: testing of asynchronous sets/resets

Most designs have some asynchronous sets or resets. Uncontrollable sets/resets can lower test coverage. This…

What’s happening at SEMICON West?

SEMICON West is happening this week, again at the Moscone Center in San Francisco. SEMICON…

How-to create comprehensive test coverage reports during hierarchical DFT

Rick Fisette – Mentor, A Siemens Business This three-part video series shows how to use…

eSilicon Masters DFT and IP test for a deep learning SiP with Tessent

eSilicon used the Tessent family of DFT solutions to solve their toughest challenges of testing…

Intel’s dramatic test quality improvement with Tessent

Intel used the Tessent cell-aware, defect-oriented test to reap stunning reductions in DDPM for an…