Event: Tessent 2023 DFT Tech Forum
Presenting silicon lifecycle solutions from Siemens EDA: Engineering a smarter future faster
Don’t miss the 2023 Design-for-Test (DFT) Tech Forum in Bengaluru, India on March 29, 2023. The focus of this year’s forum is how to use Siemens Tessent solutions to address complex SoC DFT challenges. Attendees will hear from industry experts and fellow designers about best practices that reduce DFT development time up to 50%.
The live DFT Tech Forum will focus on EDA silicon lifecycle solutions, allowing you to Engineer a Smarter Future Faster with Siemens EDA.
Tessent Vice President and General Manager, Ankur Gupta will deliver the Siemens keynote address titled “Adaptive intelligence — Proven DFT solutions that adapt to the complex challenges of today and future test and in-life requirements.” The Industry keynote, “Gates All Around: Yesterday, Today and Tomorrow” will be presented by Jais Abraham, Sr. Director of Design Engineering, and manager of the Design-For-Test group at Qualcomm India.
There are 15 sessions that alternate between Siemens experts and industry expert experience sessions. What you will learn:
- How to implement DFT in chiplets, 2.5D and 3D designs using Tessent Multi-die
- How to ensure quality, reduce risks and meet industry standards using with Tessent safety and security solutions
- How to turbo charge your network access throughput with fast IJTAG
- How a DFT architecture can support tile-based designs, saving weeks of engineering effort
- How to use Tessent Streaming Scan Network (SSN) to solve complex SoC scan distribution challenges by leveraging packetized delivery of scan test data
- How to integrate intelligent analytics infrastructure into core hardware to monitor and analyze real-world behavior
Tessent IC test, yield learning and functional monitoring solutions include best-in-class design-for-test tools and test data analytics, plus security, debug and in-life monitoring products. Come learn how Tessent solutions help ensure the highest test coverage, accelerate yield ramp and improve quality and reliability across the silicon lifecycle. Slots are limited to maximize your learning experience, so register today!