Tessent earns TSMC OIP Partner of the Year for 3DFabric collaboration

Recognition of Tessent’s excellence in next-generation system-on-chip and 3DIC design enablement. Siemens EDA takes industry…

DFT webinar: A new method to find and optimize the most effective test patterns

Choosing the most efficient test patterns and setting coverage targets has always been a challenge…

DFT and the competitive edge

Smart DFT for quality and TTM Don’t let your plans for successful new SoCs be…

Join Tessent at the VOICE Developer Conference

Tessent invites you to join us at the upcoming VOICE Developer Conference happening virtually from…

RealizeLIVE + User2User

Don’t miss these Tessent sessions at Realize LIVE + User2User event – May 26, 2021

Explore the latest DFT, operations and embedded analytics technologies at Realize LIVE + U2U 2021….

VTS 2020 best paper_Tessent

Tessent wins Best Paper award at IEEE VLSI Test Symposium

The best paper of the 2020 symposium describes a layout-friendly EDT decompressor that reduces routing…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before…

Introducing Tessent Streaming Scan Network

Slash test costs and reduce implementation effort for complex next-generation SoCs. IC engineering teams have…

Tessent’s ITC 2020 wrap-up

The International Test Conference carried on this year as a virtual event. It’s a difficult…