DFT and the competitive edge

Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at…

Video: ITC India 2020 keynote—Test community can take on silicon lifecycle challenges

The role of test is expanding from its traditional role into one that includes managing…

Best practice in scan pattern ordering for test and diagnosis

By Jay Jahangiri and Wu Yang, Mentor Graphics By creating and applying scan patterns in…

What DFT history teaches us

By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as…

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical…

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the…

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how….

Automotive Semiconductor Test

By Steve Pateras, Mentor Graphics Ensure quality and reliability in automotive ICs with the newest…