The age of AI comes to IC test automation

By Ron Press

As IC design and test become more complicated, designers need every tool to maintain a competitive edge. Electronic design automation (EDA) software has long been a key tool needed for IC design. Automation simplifies the design tasks and enables more capabilities to design better chips faster.

Now, as the world is rapidly applying artificial intelligence (AI) to myriad challenges, EDA tools are also making strategic use of AI in software across the entire IC design flow. Tools like Tessent have included machine learning (ML) and AI algorithms for years and have proven to be effective and robust. To explain the types of AI-driven automation offered in the Tessent products, you can read a new paper from Ron Press, Using AI for advances in test.

Tessent embeds three types of AI, illustrated in figure 1.

  • Adaptive—Improves existing functionality by leveraging contextual information
  • Additive—Enables new functionality by leveraging temporal information
  • Assistive—Optimizes and extends solutions by leveraging extrapolated knowledge
Figure 1. Three families of artificial intelligence employed at Siemens.

How do these types of AI in Tessent tools help you? By making the tools “smarter” for one. Rather than spending your time adjusting variables and settings, Tessent takes an algorithmic approach as much as possible. The results are not unlike what we experience with consumer electronics where many tasks that used to be onerous are now seamless.

The ML/AI features in Tessent make decisions that can be controlled and explained. Engineers need to know how a tool made any given decision and be able to take control. Tessent empowers users with optimized results and presents the trade-offs. In fact, the Tessent flow is highly customizable. With the Tessent Platform environment, you can introspect what data the tool is aware of and build custom scripts for your special needs, creating tool-level features, design rule checks, and more.

Expert systems in the Tessent tools

Expert systems are a simple form of AI that mimic the knowledge and decisions of an expert user, embedding user knowledge and decision making into the tools. Expert systems are embedded within Tessent Automatic Test Pattern Generation (ATPG) to simplify the ATPG process and post-ATPG debug.

ATPG Expert is a utility that simplifies the task of analyzing the design to determine the best parameters to set for an ATPG run. The goal is to optimize coverage and pattern count automatically. The settings include which clocks to pulse, abort limits, contention checks, sequential depth and more. ATPG Expert can adapt during an ATPG session and adjust the parameters as needed.

Fault grouping for automated debug

After ATPG, you might need to run experiments to debug missing coverage. Additional data is automatically embedded during the run to help with debug.  so after ATPG, you can see a summary of the types of fault categories and coverage impact without doing additional tests. Tessent’s GUI application, Tessent Visualizer, presents the summary of coverage loss due to library models, capture clocks, and hierarchical instances and modules.

ML trends in scan fail data

Yield has a direct impact on profitability, so even small improvements in yield ramp and mature yield is worth fighting for. ML/AI is good at finding yield limiters that are hidden from humans by analyzing large data sets. Tessent first deployed an expert system for scan diagnosis about 15 years ago in Tessent Diagnosis. It uses probability-based diagnosis to group faults based on known/expert characteristics, which filters candidates into the most likely suspects.

Tessent uses unsupervised ML (with limited guidance) to improve accuracy and resolution of yield limiters. Tessent also uses this form of ML for profiling-based chain diagnosis and logic diagnosis, root cause deconvolution (RCD) to remove noise in diagnosis results, and for population-based statistical diagnosis.

The use of AI in scan diagnosis works as a digital twin for physical failure analysis. Applying unsupervised machine learning to massive amounts of failure data helps designers use fewer resources and get to the right answers faster.

A new DFT architecture

When designing a full SoC, there are many tradeoffs related to the DFT architecture and it can take many iterations as the core designs evolve to reach an effective architecture. The tradeoffs include deciding which set of cores to test in parallel and how to use available IOs.  These tradeoffs must be made even while core features like scan channel requirements and pattern set sizes are changing. Setting up this DFT architecture has a direct impact on time to market and once set, it is usually static.

Tessent addresses this with the Tessent Streaming Scan Network (SSN), a DFT architecture that removes the difficult tradeoffs (figure 2). SSN uses a packetized data delivery mechanism for scan data. Any size SSN bus can be used to deliver data to any size scan channels at various cores, eliminating iterations to balance IO to cores, or even to have a top-level test access mechanism (TAM).

Figure 2. SSN removes the need to trade off and optimize core scan channels/patterns with the embedding and IO pins available.

The benefits of SSN are hard to overstate. Some well-known industry leaders have reported as much as 10x productivity improvement after switching to SSN (Côté, et al., 2020). For more on the benefits of SSN, read the new paper from Ron Press, Using AI for advances in test.

DFT tools that learn from and guide users

The use of ML and AI in Tessent DFT tools is expanding to include training DFT tools to learn from users and guide them. An example is our partnership with PDF Solutions to find layout patterns that are prone to fail. This big data analysis approach can improve yield by an additional 1-3%.

ML can optimize ATPG by learning certain characteristics of a design. The goal is to compare the ATPG to previous designs or the same design before ECOs to see what has changed, making a full ATPG run unnecessary.

We have more opportunities to help automate DFT, ATPG, and diagnosis to improve the entire IC test flow. Increasing the efficiency of IC test becomes even more important for businesses that are short staffed of skilled DFT engineers or have fast time to market requirements. Providing help with flow/methodology guidance, finding the optimal configurations for DFT, compression and ATPG should provide meaningful improvements to design productivity. Tessent continues to develop solutions that simplify and automate design tasks algorithmically.

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This article first appeared on the Siemens Digital Industries Software blog at