Tessent Silicon Lifecycle Solutions

What is silicon lifecycle management?

The next step in IC test and monitoring by Aileen Ryan – Senior Director of…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before…

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical…

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the…

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how….

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically…

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier….

Test Points are Trending

By Ron Press, Mentor Graphics Mentor’s EDT test points slash pattern count, test time and…

Using EDT Test Points to reduce test time and cost

By Vidya Neerkundar, Mentor Graphics New EDT Test Points are the next big thing in…