The age of AI comes to IC test automation

Learn how artificial intelligence (AI) is advancing IC test and yield analysis.

Register for the SAFE Forum: Siemens presents safety island and more

Learn about using a safety island for effective control and monitoring of automotive ICs.

Image showing the architecture of a bus-based packetized scan test delivery system. Each core’s DFT can be designed independently and with the most optimal compression configuration.

Video: Generating clocks in Tessent Streaming Scan Network

Learn about generating clocks in Tessent Streaming Scan Network (SSN) in this presentation and Q&A recorded at the 2023 U2U North America.

Don’t Miss Silicon Lifecycle Solutions at U2U

Don’t miss the exciting lineup of Tessent Test and Embedded Analytics presentations at U2U North America on A[ril 13, 2023.

On-demand Webinar: Faster DFT, better results

Learn about faster DFT and better results using the bus-based packetized test of Tessent Streaming Scan Network.

DFT for tile-based design

How to master DFT for tile-based designs

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

Webinar: Smarter DFT architecture for advanced SoCs

Leonardo DaVinci said that “Simplicity is the ultimate sophistication.” Semiconductor design is a very complex process, and every step of…

Tessent Silicon Lifecycle Solutions

What is silicon lifecycle management?

The next step in IC test and monitoring by Aileen Ryan – Senior Director of Portfolio Strategy, Siemens Digital Industries…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…