DFT for tile-based design

How to master DFT for tile-based designs

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

Webinar: Smarter DFT architecture for advanced SoCs

Leonardo DaVinci said that “Simplicity is the ultimate sophistication.” Semiconductor design is a very complex process, and every step of…

Tessent Silicon Lifecycle Solutions

What is silicon lifecycle management?

The next step in IC test and monitoring by Aileen Ryan – Senior Director of Portfolio Strategy, Siemens Digital Industries…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.

Take scan test out of the critical path

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.  

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume

A flexible flow for inserting embedded compression logic in RTL

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier.