Don’t Miss Silicon Lifecycle Solutions at U2U

By Tessent Solutions

Join us at U2U 2023, the Siemens EDA free, on-day event featuring innovative keynotes from industry leaders, enriching technical sessions and opportunities to connect to network with colleagues and peers in the global user community.

North America: April 13, 2023 in Santa Clara, California

At the Siemens EDA User2User symposium, you’ll hear about real-world experiences from top designers using the Tessent solutions to debug & optimize SoCs, solve yield problems, find bridge defects, test 3D ICs, and use bus-based packetized test to radically improve DFT planning, implementation, and quality.

Here’s the line up of presentations:

Debug & optimization strategy in tomorrow’s storage technology, from Richard Bohn, Seagate.

Photo of Richard Bohn, presenting at U2U

Storage technology is a key enabler for today’s data economy. Storage providers need to deliver efficiency, high availability, frictionless data mobility and low-latency delivery. That’s why Seagate has developed RISC-V technology for next-generation proprietary storage ICs.

One of the challenges was to establish a debug and optimization strategy to optimize the performance of both hardware and firmware. The Seagate team relied on the standards-compliant debug and trace technology from Siemens (formerly UltraSoC) to gain a deep understanding of the performance of their hardware and code. This presentation outlines Seagate’s fundamental challenges, examines why traditional code instrumentation techniques are inadequate for high-performance, real-time control systems such as storage controllers, and looks at how Siemens’ Enhanced Trace Encoder—the only commercially-available trace solution compliant to the RISC-V Trace Specification—helps to address these challenges.

Break Through Yield Barriers with Siemens and PDF Solutions, from Thomas Zana, PDF Solutions and Jayant D’Souza, Siemens EDA.

Photo of Thomas Zanon

Accelerating yield ramp calls for new solutions that leverage the best technologies on the market. In a powerful collaboration, Siemens and PDF Solutions integrate machine learning for logic in Siemens Tessent YieldInsight and memory diagnosis in Tessent SiliconInsight with the capabilities of PDF Solutions’ Exensio® Manufacturing Analytics platform to provide a comprehensive yield and failure analysis solution. This presentation will introduce this solution and highlight its benefits.

Targeted Screening of Bridge Defects on Automotive Designs, from Saidapet Ramesh, NXP.

Photo of Saidapet Ramesh

A combination of ATPG scan SA, TD, CA and timing-aware SDD patterns have been used primarily to guarantee zero defects on automotive designs. With the ever-shrinking process nodes, the BEOL layers are closer together making them more susceptible to bridging defects. This motivated NXP to evaluate new Defect-Oriented-Tests (DOT) for BEOL layers, which includes targeted Inter-Connect Bridge (ICB) and Inter-Connect Open (ICO) ATPG patterns. This paper presents the summary of findings from multiple designs, which confirmed the unique test quality added by Inter-Connect Bridge patterns.

3D IC DFT flow development experience using Tessent Multi-die, from Saket Goyal, Broadcom.

Photo of Saket Goyal

The transition from monolithic ICs to 3D stacked chiplets in a System-in-Package (SiP) calls for several enhancements to existing DFT workflows. We discuss the requirements and considerations for developing a DFT flow for 3D IC, along with challenges and solutions. A hierarchical DFT methodology was extended to include the 3D stack by introducing the IEEE 1838 test access architecture. The internal scan architecture for each chiplet was limited to traditional EDT while Streaming Scan Network (SSN) was used for efficient packetized scan delivery to the scan interface of each chiplet. This paper presents the summary of our experience using Tessent Multi-die.

System-on-Chip ATPG with Tessent SSN, from Taoi Vo, Intel.

Photo of Toai Vo

Automatic Test Pattern Generation (ATPG) and verification are the most important tasks to ensure SoC quality, reliability and diagnosis. Siemens Tessent SSN (Streaming Scan Network) solves challenges in scan I/O scalability, reusability and automation with traditional ATPG. SSN provides a very easy transition from traditional EDT channel-based ATPG to packet-based ATPG with SSN. In this presentation, we will share the successful accomplishments of our first silicon design with Tessent SSN ATPG.

Common Scan Clock Generation Methods in SSN, from Ron Press, Siemens EDA Tessent.

Photo of Ron Press

This presentation outlines various scan clock generation methods available in Siemens Scan Streaming Network (SSN) technology and how Streaming Scan Host Node (SSH) can be configured to use one method over the other. The presentation also provides guidelines on the use case scenarios of each method and compares their advantages. Some of the advantages of SSH clock generation methods include easing burden on timing closure and clock balancing of the scan clocks to achieve maximum shift rate.

Don’t miss the opportunity to hear these presentations and connect with fellow Tessent users.

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This article first appeared on the Siemens Digital Industries Software blog at