Shift Left in DFT Design

Tessent™ RTL Pro software automates the analysis and insertion of Tessent VersaPoint™ test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading DFT tools by providing unique functionality that helps customers shorten design turnaround time and
accelerate time-to-market.

No-compromise packetized test improves DFT efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test…

Google and Tessent Streaming Scan Network at ISTFA 2024

Technology advancements have led to a significant increase in system-on-chip (SoC) complexity, necessitating the careful optimization of DFT techniques to…

Enhance safety with Tessent

Enhance safety with Tessent

Learn how to ensure safety for automotive ICs with Tessent solutions from Siemens EDA.

The age of AI comes to IC test automation

Learn how artificial intelligence (AI) is advancing IC test and yield analysis.

Video: Leveraging the RISC-V efficient trace (E-Trace) standard

Learn more about using the RISC-V efficient trace standard for non-intrusive, full-speed and system-level visibility.

Three ways to slash AI chip TTM with advanced DFT and silicon bring-up

Advanced EDA technology eases AI chip development.

Picture of James Pickford at the Elektra awards banquet.

Awarding excellence: Siemens’ James Pickford wins BrightSparks award

Siemens’ James Pickford wins BrightSparks award.

RISC-V | Solving bus and software deadlock problems in complex SoCs

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.