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DFT for tile-based design

How to master DFT for tile-based designs

October 23, 2022

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

By Tessent Solutions
2 MIN READ

Video: ITC India 2020 keynote—Test community can take on silicon lifecycle challenges

September 15, 2020

The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To…

By Tessent Solutions
3 MIN READ