DFT webinar: A new method to find and optimize the most effective test patterns

Choosing the most efficient test patterns and setting coverage targets has always been a challenge and becomes even more daunting…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…

What DFT history teaches us

What DFT history teaches us

By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

Ensure defect-free automotive ICs with the Hybrid TK/LBIST solution that also finds faults in the DFT logic

By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.

Take scan test out of the critical path

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.  

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume

A flexible flow for inserting embedded compression logic in RTL

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier.