The age of AI comes to IC test automation

Learn how artificial intelligence (AI) is advancing IC test and yield analysis.

Professional Engineer Works on a Computer with a 3D CAD Software and Tests the Electric Car Chassis Prototype with Wheels, Batteries and Engine Standing in a High Tech Development Laboratory.

Ensure IC quality with Tessent

Tessent software and IP ensures semiconductor companies can achieve the highest IC quality. Learn how.

Image showing the architecture of a bus-based packetized scan test delivery system. Each core’s DFT can be designed independently and with the most optimal compression configuration.

Video: System-on-chip ATPG with Tessent SSN

Learn how Intel adopted Tessent SSN packet-based ATPG and reduced test time by 34% in this video recorded at the 2023 North America U2U symposium.

Video: Developing DFT flow for 3D IC at Broadcom

Learn how Broadcom used Tessent Multi-die to build a 3D IC flow in this video recorded at the 2023 North America U2U symposium.

Don’t Miss Silicon Lifecycle Solutions at U2U

Don’t miss the exciting lineup of Tessent Test and Embedded Analytics presentations at U2U North America on A[ril 13, 2023.

DFT webinar: A new method to find and optimize the most effective test patterns

Choosing the most efficient test patterns and setting coverage targets has always been a challenge and becomes even more daunting…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…

What DFT history teaches us

What DFT history teaches us

By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago