Tessent software and IP ensures semiconductor companies can achieve the highest IC quality. Learn how.
Learn how Intel adopted Tessent SSN packet-based ATPG and reduced test time by 34% in this video recorded at the 2023 North America U2U symposium.
Learn how Broadcom used Tessent Multi-die to build a 3D IC flow in this video recorded at the 2023 North America U2U symposium.
Don’t miss the exciting lineup of Tessent Test and Embedded Analytics presentations at U2U North America on A[ril 13, 2023.
Choosing the most efficient test patterns and setting coverage targets has always been a challenge and becomes even more daunting…
To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…
The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…
By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago
By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
