The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These free, on-demand seminars were recorded live,and feature the latest and most talked-about DFT and yield-improving technologies in the industry. They are now all available on-demand.
Some of our most popular seminars cover faster silicon bring-up, improved debug productivity, volume diagnosis, and how to create more effective test pattern sets. Each lasts no more than an hour, so you can easily brush up on the hottest technologies.
This seminar, from Tessent and Teradyne, covers the current and upcoming challenges for bring-up of complex SoCs, shows how industry partnerships spurred the development of EDA software and ATE hardware tools that work together, and demonstrates through IJTAG and MBIST case studies how to reduce bring-up from weeks to immediate results
This skills-focused course covers how to solve the challenges of the most time-consuming DFT debug tasks. Tessent Visualizer helps you find and trace to objects in large cones of logic >100x faster than traditional tracing methods. You will learn how to use the intuitive schematic features and the powerful table-driven search engine to debug test coverage and DRC violations faster.
This seminar covers the basics of scan test and can diagnosis and how the new dynamic partitioning technology makes the best use of your existing hardware resources to significantly improve the throughput of volume scan diagnosis.
Tessent DFT – Critical area-weighted pattern optimization: Automation to choose the most effective patterns
This course introduces a new ATPG solution that can calculate the critical-area effectiveness of each test pattern. Knowing the likelihood of detecting defects based on their critical area, combined with pattern sorting between various pattern sets, lets users choose the most effective test patterns to apply.