No-compromise packetized test improves DFT efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test…

Google and Tessent Streaming Scan Network at ISTFA 2024

Technology advancements have led to a significant increase in system-on-chip (SoC) complexity, necessitating the careful optimization of DFT techniques to…

Maximizing SoC Performance: The Role of Embedded Software and Functional Monitors

In the rapidly evolving landscape of System on Chip (SoC) development, the demand for effective debugging and optimization is becoming…

The age of AI comes to IC test automation

Learn how artificial intelligence (AI) is advancing IC test and yield analysis.

RISC-V – It’s not just about the core, it’s also about the system

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

Debugging a RISC-V processor requires integrated hardware and software tools

Debugging a RISC-V processor requires integrated hardware and software tools

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

The future of in-system testing for automotive safety

Suppliers of IP for automotive applications must ensure their IP blocks are ISO 26262 compliant. Siemens has the solutions for automotive safety and reliability.

Event: Tessent 2023 DFT Tech Forum

Attend the 2023 DFT Tech Forum to learn how Tessent silicon lifecycle solutions solve your complex SoC DFT challenges.

Typical allocation of functional safety within an automotive SoC.

Webinar: Meet the Challenges of ISO 26262 with Tessent Test Solutions

Register Now! Tune in on June 9, 2022 at 11:00 am (pacific daylight time) to learn how to use Tessent…