Read the 2020 ITC paper: Tessent Streaming Scan Network

At the 2020 International Test Conference, a paper by scientists from Siemens Digital Industries Software and Intel, describes how the…

Tessent Silicon Lifecycle Solutions

What is silicon lifecycle management?

The next step in IC test and monitoring by Aileen Ryan – Senior Director of Portfolio Strategy, Siemens Digital Industries…

Tessent LBIST with Observation Scan Technology Wins Elektra Design Tool Award 2020

A Tessent technology was awarded the 2020 Elektra Design Tools and Development Software Award from a crowded field of nominated…

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…

Pattern Matching in Test and Yield Analysis

Pattern Matching in Test and Yield Analysis

By Geir Eide and Jonathan Muirhead Analyzing fail data with pattern matching helps companies identify yield limiters faster to increase…

Test Pattern Retargeting in 3D SICs using an IEEE 1687 based 3DFT architecture

Test Pattern Retargeting in 3D SICs using an IEEE 1687 based 3DFT architecture

Retarget your 2D test to 3D with IJTAG

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Is DFT a barrier to tapeout? Time to consider going hierarchical.