Video from DAC: Tessent functional safety and automotive test solutions

Learn how to use Tessent test solutions for functional safety and automotive applications. This video was recorded at the 2023 Design Automation Conference.

Video from DAC: IC lifecycle monitoring with Tessent Embedded Analytics

Learn how Tessent Embedded Analytics accelerates SoC debus and ongoing silicon monitoring though the IC lifecycle. This video was recorded at the 2023 Design Automation Conference.

Video from DAC: DFT for 2.5D and 3D designs with Tessent Multi-die

Learn how Tessent Multi-die software helps implement design-for-test structures for 2.5D and 3D designs. This video was recorded at the 2023 Design Automation Conference.

Video: STMicroelectronics improves test quality with Tessent defect-oriented test

Learn how STMicroelectronics used Tessent defect-oriented test to improve the quality of devices for their automotive customers. This video was recorded at the 2023 European User2User conference.

Video: Reducing test pattern count with testpoints

Learn how Qualcomm reduced test pattern count using Tessent testpoint technology. This video was recorded at the 2023 European User2User conference.

Video: Testonica uses Tessent IJTAG to implement an FPGA-based reference system

Learn how Testonica used Tessent to implement an FPGA-based reference system for pre-silicon evaluation and validation of a target IJTAG infrastructure. This video was recorded at the 2023 European User2User conference.

Video: NXP Semiconductors success with Tessent for in-system test for ISO 26262

Learn how NXP Semiconductors implemented in-system test for automotive devices using Tessent, recorded at the 2023 European User2User conference.

Video: Intel uses Tessent SSN for IC test and bring-up

Hear about Intel’s use of Tessent SSN for test and silicon bring up, recorded at the 2023 European User2User conference.

Image showing the architecture of a bus-based packetized scan test delivery system. Each core’s DFT can be designed independently and with the most optimal compression configuration.

Video: System-on-chip ATPG with Tessent SSN

Learn how Intel adopted Tessent SSN packet-based ATPG and reduced test time by 34% in this video recorded at the 2023 North America U2U symposium.