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Re-use high-speed IOs/SERDES for scan test with IEEE 1149.10

Learn about how Mentor and our partners, Advantest and Teradyne, are getting behind the IEEE…

Test technologies enabling AI

At the Silicon Valley DFT and Test Conference in Santa Clara, CA on October 23,…

50 Years of International Test Conference

In 1970, the Beatles officially split, Apollo 13 narrowly averted disaster, paisley and stripes somehow…

Video tutorial: How to Increase Volume Scan Diagnosis Throughput by 10X

Performing volume scan diagnosis on today’s large, advanced node designs puts outsized demands on turn-around-time…

Employing a Hierarchical Methodology for SoC Testing

When faced with a complex problem, engineers often employ a divide and conquer approach to…

Automotive electronics innovations in test quality

The rapid development of advanced driver assistance systems and autonomous vehicles has grabbed the world’s…

Maximize diagnosis throughput with Dynamic Partitioning

Charged with the task of improving yield, product engineers need to find the location of…

DFT for AI chips draws a crowd at ITC India tutorial

At the recently concluded ITC India conference, Mentor experts presented the two highest-attended tutorials. One…

How-to implement hierarchical DFT on Arm cores

The new reference flow jointly developed by Arm and Mentor for hierarchical DFT and ATPG…