The Tessent silicon lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from the design-for-test phase through continuous IC monitoring. Tessent helps customers address their debug, manufacturing test, yield, functional safety, IC security, and optimization requirements for today’s most complex SoCs.
How to master DFT for tile-based designs
Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.