Tessent Solutions

The Tessent silicon lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from the design-for-test phase through continuous IC monitoring. Tessent helps customers address their debug, manufacturing test, yield, functional safety, IC security, and optimization requirements for today’s most complex SoCs.

Filter by:

Latest posts

DFT for tile-based design

How to master DFT for tile-based designs

October 23, 2022

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

By Tessent Solutions
2 MIN READ
A new way of measuring heterogeneous SoC performance

Explore a new way to measure heterogenous SoC performance at the Linley Fall Processor Conference

October 22, 2022

Join Siemens at the Linley Fall Processor Conference, the two-day event focusing on processors and IP cores used in embedded, communications, automotive, IoT,
and server designs.

By Tessent Solutions
2 MIN READ

Tessent at ISTFA 2022

October 21, 2022

Join Tessent at the 48th International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community.

By Tessent Solutions
< 1 MIN READ

Cornell University: Building Sparse Linear Algebra Accelerators with HLS

October 14, 2022

Sparse linear algebra (SLA) operations are essential in many applications such as data analytics, graph processing, machine learning, and scientific…

By Mathilde Karsenti
< 1 MIN READ

Efficient and effective DFT for 3D stacked die

August 22, 2022

Yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs.

By Martin Keim
6 MIN READ

Chip data joins the party with Tessent Host Services software

June 23, 2022

Siemens’ Tessent Embedded Analytics IP and software, Host Services software opens the lines of communication with your chip and brings SLS one step closer to reality.

By Tessent Solutions
2 MIN READ

Customers Share Their Experiences Using High-Level Synthesis

May 13, 2022

High-Level Synthesis (HLS) has never been more in demand for chip design. In fact, it could be said that the…

By Mathilde Karsenti
< 1 MIN READ
Typical allocation of functional safety within an automotive SoC.

Webinar: Meet the Challenges of ISO 26262 with Tessent Test Solutions

May 4, 2022

Register Now! Tune in on June 9, 2022 at 11:00 am (pacific daylight time) to learn how to use Tessent…

By Tessent Solutions
< 1 MIN READ

Power: Front & Center of the Silicon Design Process

April 6, 2022

Power is one of the most critical design metrics today, but it still is an afterthought in far too many…

By Mathilde Karsenti
2 MIN READ