Latest posts

A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Read the entire article on TechDesignForum originally published…

Watch videos from the AI Hardware Summit 2021

The AI Hardware Summit wrapped up on 15 September, 2021 at the Computer History Museum in Mountain View, CA. The…

Automotive electronics solutions at AESIN Conference 2021

A successful Automotive Electronics Innovation (AESIN) conference at the UK’s National Motorcycle Museum in Solihull wrapped up on 16 September…

Webinar: Reversible Scan Chain Technology Improves Diagnosis Resolution by 4X

Join Siemens and Qualcomm experts for a live, one-hour, online seminar: A Novel Reversible Scan Chain Technology that Improves Chain…

Tessent scan diagnosis at IPFA

IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2021) is a virtual event this year,…

DFT webinar: A new method to find and optimize the most effective test patterns

Choosing the most efficient test patterns and setting coverage targets has always been a challenge and becomes even more daunting…

Tessent at 2021 Automotive Electronics Innovation (AESIN) Conference

Siemens is a headline sponsor of the 2021 Automotive Electronics Innovation (AESIN) Conference taking place at the UK’s National Motorcycle…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…

Welcome to: HLS Design & Verification Blog

Welcome to: HLS Design & Verification Blog

This blog will cover next generation High-Level Synthesis (HLS) design and verification methodologies and techniques. Actual users will be talking…