International Test Conference 2021

ITC 2021 logo

Join Siemens at the International Test Conference 2021 (ITC) to be held virtually from October 10-15, 2021. We’ll be showcasing technologies that address the biggest challenges facing the semiconductor industry today: technology scaling; design scaling; and system scaling. And we’ll be looking at the key role of test in creating silicon lifecycle solutions that make the industry more responsive and resilient in a time of unprecedented global change. 

Register now

Diamond Supporter Event: The industry’s transition to packetized test 

Tuesday, October 12 at 11:00 am PDT.  

A lot has happened since ITC 2020, when Tessent introduced the first commercial full-flow implementation of packetized scan test: Streaming Scan Network (SSN).

In this year’s ITC Diamond Supporter event, hear directly from some of our industry partners about how they are leveraging SSN in their next designs. You can also hear from Tessent technologists about what’s next for this transformative technology that not only solves the problems of today, but also creates a foundation for future 3D DFT, high-bandwidth scan test, in-system test, and beyond.  

“Last year, Siemens precipitated the industry’s move from traditional DFT architectures to packetized test, with the introduction of Tessent SSN — the first commercial, full-flow implementation of packetized scan test DFT technology.”

Geir Eide, director, product management for Tessent DFT products

Siemens Virtual Booth in the Networking Lounge

Visit the Siemens virtual theater booth in the networking lounge for presentations by test experts, customers and partners on topics including:  

  • SSN and packetized test 
  • New products and technologies  
    • ATPG Boost improves coverage, cost and throughput  
    • Reversible chain diagnosis accelerates yield ramp  
    • Tessent SiliconInsight High Performance speeds chip bring-up  
  • Low power and IDDQ 
  • Test time and volume 
  • Flexible DFT architecture 
  • Low risk hierarchical flow 
  • 2.5/3D DFT 
  • Improving test quality with critical area pattern optimization 
  • Automotive safety island 

Check in at the theater for the presentation schedule. 

Network in our virtual technology booths for more information. Our experts are here to answer your questions. 

  • Tessent DFT – New technologies, methodologies and insights from the leader in semiconductor test  
  • Tessent Operations – Solutions for bring-up, debug, characterization and yield management 
  • Beyond Test – Lifecycle solutions, safety, security and automotive 

Schedule a Meeting

Session Papers and Tutorials

Tutorial 3 – AI Chip Technologies and DFT Methodologies
Presented by Lee Harrison, Piero Orlando, Jay Jahangiri, and Geir Eide

Tutorial 5 – Mixed-Signal DFT and BIST: Trends, Principles and Solutions
Presented by Stephen Sunter

Session 1C – 3DIC Test Challenges, Trends and Solutions – an EDA perspective
Presented by Wu Yang

Session 4C – On Reduction of Deterministic Test Pattern Sets, J. Tyszer, Poznan University of Technology; J. Rajski, S. Milewski, S. Eggersgluess

Session 4D – Memory Testing Embedded Tutorial
Presented by Raghav Mehta, Benoit Nadeau-Dostie, Jongsin Yun

Co-located Events

Tessent is a proud supporter of the IEEE Automotive Reliability, Test & Safety virtual workshop and the first IEEE International Workshop on Silicon Lifecycle Management workshop happening on October 14 – 15.  Register Now through the ITC registration page.

Tessent will be presenting at the first IEEE International Workshop on Silicon Lifecycle Management workshop happening October 14 – 15. All sessions are listed in Pacific Time

October 14th, 4:20 PM

Unprecedented scaling demands have changed the face of EDA, presented by Ron Press.

October 15, 10:45 AM

Using Silicon Lifecycle Management to Monitor Aging Effects on Automotive Electronics, presented by Lee Harrison.

October 15, 12:45 AM

Use of Functional monitoring for Inlife latency reduction, presented by Aileen Ryan.

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