Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

May 14, 2024

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

By Keith Felton
2 MIN READ
Image of a chip with text that says: High Bandwidth Memory integration

Managing the complexities of High Bandwidth Memory integration in high-performance computing

March 12, 2024

The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI…

By Keith Felton
2 MIN READ
Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

February 21, 2024

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

By John McMillan
4 MIN READ

Latest posts

IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

August 18, 2022

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

By Keith Felton
2 MIN READ
Evolution of 3D IC Architecture and the impact to design flows

Evolution of 3D IC Architecture and the impact to design flows

August 11, 2022

In our last blog about 3D IC, we discussed the models chiplet vendors need to provide System-in-Package (SiP) integrators to…

By Heather George
10 MIN READ
3D IC and the system-technology co-optimization (STCO) approach

3D IC and the system-technology co-optimization (STCO) approach

August 3, 2022

Semiconductor engineers aim to deliver best-in-class devices despite technology scaling and cost limitations of monolithic integrated circuit (IC) design. To…

By anthonymastroianni
2 MIN READ

What’s the current state of 3D IC design?

July 20, 2022

In the first podcast about 3D IC heterogeneous integration, we talked about the disaggregation of once monolithic implementation architectures into…

By Heather George
9 MIN READ

Getting your metal fill right

July 14, 2022

If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then…

By Keith Felton
2 MIN READ
The beginner’s guide to 3D IC

The beginner’s guide to 3D IC

July 7, 2022

As consumer electronic devices grow increasingly connected, intelligent and advanced, designers need new methodologies such as 3D IC to address…

By Heather George
17 MIN READ

Semiconductor package design market trends: 2023 forecast from Siemens EDA

June 29, 2022

Semiconductor package design industry in 2023 expects to see accelerated growth of heterogeneous integration resulting emergence and adoption of new technology.

By Keith Felton
3 MIN READ