Semiconductor Packaging

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Latest posts

Five Key Trends of Co-Packaged Optics (CPO) in 2026

February 5, 2026

For years, data-center performance scaled by following a familiar playbook: faster GPUs, higher SerDes rates, and increasingly aggressive board designs….

By Tony Mastroianni

5 MIN READ

Six Key Trends Redefining 3D IC Packaging in the AI Era

February 5, 2026

Some say we are officially in the Post-Moore’s Law world.  Moore himself closed his seminal paper by mentioning the “day…

By Pratyush Kamal

5 MIN READ

Verifying your 2.5/3D IC device assembly level netlist

February 4, 2026

In this blog we will introduce a new way to verify your 2.5/3D IC device assembly level netlist using formal verification that can exhaustively verify all interconnections between the chiplet blocks.

By Keith Felton

3 MIN READ

Thermal management in 3D IC: Challenges, modeling and design strategies

January 26, 2026

You are likely here because thermal issues have become the primary constraint shaping your 3D IC design decisions. As 3D integration pushes more performance into smaller footprints, thermal…

By Tova Levy

5 MIN READ

Ensure 3D IC Multiphysics Reliability for AI Systems at Scale

January 18, 2026

Every new generation of AI systems pushes SoC design teams closer to the end of Moore’s Law. The core question…

By Tova Levy

6 MIN READ

System-technology co-optimization in 3D IC design

What Lies Ahead for System-Technology Co-Optimization (STCO) in 2026

January 15, 2026

The race to build ever more powerful and energy-efficient AI chips has been underway for years, but 2026 is shaping…

By Per Viklund

5 MIN READ

What is 3Dblox?

January 13, 2026

If you have not heard of it before, 3Dblox is an emerging standard that was first created by TSMC but is now managed by IEEE.

By Keith Felton

2 MIN READ

3D IC thermal challenges and trends 2026

Key Thermal Advances Driving Next-Gen AI Chip Design in 2026

December 15, 2025

AI is hot — literally. As we bid farewell to a transformative year of 2025, there’s no doubt that the AI chip underwent substantial changes. As AI compute is pushing…

By Andras Vass-Varnai

3 MIN READ