Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows…

Package verification just took a big step forward…

By Armen Asatryan and John Ferguson Over a decade ago, Calibre Design Solutions moved early into defining and building physical…

Fix first, finish faster!

By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit…

Time is money…so why waste it on bad data?

By James Paris Last Saturday was my son’s birthday and we had many things to do to get ready for…

Shining a light on silicon photonics verification

By John Ferguson, Omar ElSewefy, Nermeen Hossam, Basma Serry We’re all fascinated by light. Light beams shooting from aliens’ eyes,…

Using Automated Pattern Matching For SRAM Physical Verification

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

Are You (Really) Ready for Your Next Node?

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?

All Together Now: FOWLP in the Foundry

All Together Now: FOWLP in the Foundry

By John Ferguson, Mentor Graphics FOWLP design popularity is driving foundries to develop in-house FOWLP flows. How will that affect…