Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…

Are Three Eyes Better Than Two?

By David Abercrombie, Mentor Graphics Error analysis in triple patterning is challenging, but a pyramid…

Balancing on the Color Density Tightrope

By David Abercrombie Potential pitfalls and available solutions….

Self-Aligned Double Patterning, Part Deux

By David Abercrombie, Mentor Graphics Part 2 of a walk-through of the SADP process.  …

Sign-off lithography simulation and multi-patterning must play well together

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography…

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than…

What about MEMS?

By Carey Robertson, Mentor Graphics With circuit performance driven by capacitance values, accurate calculations are…

A Look Behind the Mask of Multi-Patterning

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning…