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Design Rule Checking for Silicon Photonics

Design Rule Checking for Silicon Photonics

November 17, 2015

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC

By Calibre IC Design & Manufacturing
9 MIN READ
Case Studies in Double-Patterning Debug: Part One

Case Studies in Double-Patterning Debug: Part One

September 15, 2015

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious

By Calibre IC Design & Manufacturing
10 MIN READ
Custom Layout Designers Need New Tools for New and Expanding Markets

Custom Layout Designers Need New Tools for New and Expanding Markets

July 1, 2015

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your time-to-tapeout while still ensuring high-quality…

By Calibre IC Design & Manufacturing
4 MIN READ
Rule Deck Comparison Doesn’t Have to be Difficult

Rule Deck Comparison Doesn’t Have to be Difficult

May 19, 2015

By Saunder Peng Comparing results from different rule decks can be frustrating. Learn how you can use a chip finishing…

By Calibre IC Design & Manufacturing
5 MIN READ
2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

March 2, 2015

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than just fixing DRC errors as…

By Calibre IC Design & Manufacturing
6 MIN READ
The Route to Faster Physical Verification and Better Designs

The Route to Faster Physical Verification and Better Designs

February 24, 2015

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff engine instead of a limited…

By Calibre IC Design & Manufacturing
4 MIN READ