Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…

By Design With Calibre

4 MIN READ

More Than Moore: Finally Crossing the Chasm?

February 15, 2016

By Michael White, Mentor Graphics Will fan-out wafer-level packaging be the impetus that pushes 3D-IC into mainstream acceptance?

By Design With Calibre

6 MIN READ

An Automated Solution for Voltage-Aware DRC

February 2, 2016

By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to comply with voltage-aware DRC spacing…

By Design With Calibre

4 MIN READ

Resetting Expectations on Multi-Patterning Decomposition and Checking Part 2

January 25, 2016

By David Abercrombie, Mentor Graphics Triple and quadruple patterning can baffle even the most experienced designers. David Abercrombie has some…

By Design With Calibre

12 MIN READ

Electromigration and IC Reliability Risk

January 19, 2016

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures…

By Design With Calibre

5 MIN READ

You’re Not Alone

January 12, 2016

By Srinivas Velivala, Mentor Graphics Calibre How-To videos replace your roadblocks with fast solutions for tricky verification problems

By Design With Calibre

4 MIN READ

Resetting Expectations on Multi-Patterning Decomposition and Checking

December 28, 2015

By David Abercrombie, Mentor Graphics Some common misconceptions about multi-patterning processes and just how they work.

By Design With Calibre

9 MIN READ

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…

By Design With Calibre

5 MIN READ

Correct by Construction and Other Myths

December 8, 2015

By Joseph Davis, Mentor Graphics Is “correct by construction” a myth?

By Design With Calibre

5 MIN READ