Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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Simplify and speed up early floorplan verification with incremental interface DRC

Simplify and speed up early floorplan verification with incremental interface DRC

February 13, 2018

By James Paris – Mentor, A Siemens Business In early floorplan verification, incomplete blocks produce numerous interface errors. Incremental interface…

By Design With Calibre
3 MIN READ
Establishing a reliability baseline provides confidence and consistency

Establishing a reliability baseline provides confidence and consistency

February 6, 2018

By Matthew Hogan – Mentor, A Siemens Business Design companies must establish baseline robustness and reliability criteria throughout the entire…

By Design With Calibre
3 MIN READ
Get to yield ramp faster…even with new design styles

Get to yield ramp faster…even with new design styles

January 30, 2018

By Wael Manhawy and Joe Kwan – Mentor, A Siemens Business Having trouble ramping yield for new, unproven design styles? Experiments…

By Design With Calibre
3 MIN READ
HDAP connectivity verification—what’s your solution?

HDAP connectivity verification—what’s your solution?

January 23, 2018

By Tarek Ramadan – Mentor, A Siemens Business New HDAP designs like FO-WLP require package-level connectivity verification tools and processes….

By Design With Calibre
3 MIN READ
What’s New in Multi-Patterning?

What’s New in Multi-Patterning?

January 17, 2018

If you work with multi-patterning technology, you know it is a constantly-evolving process. From the addition of new multi-patterning techniques…

By Design With Calibre
2 MIN READ
Tiny Chips, Big Challenges: Full-Chip Electrical Reliability

Tiny Chips, Big Challenges: Full-Chip Electrical Reliability

January 9, 2018

Need to ensure your chip performs in the real world? The Calibre PERC reliability platform provides fast, accurate, verification for…

By Design With Calibre
3 MIN READ
Can machine learning and neural networks accurately predict post-deposition profiles for CMP modeling?

Can machine learning and neural networks accurately predict post-deposition profiles for CMP modeling?

January 3, 2018

By Ruben Ghulghazaryan and Jeff Wilson – Mentor, A Siemens Business We experimented with machine learning and neural networks for…

By Design With Calibre
3 MIN READ
Waiver headaches? We have a cure for that…

Waiver headaches? We have a cure for that…

December 27, 2017

By James Paris – Mentor, A Siemens Business Creating a standardized IP waivers database to deliver with physical IP libraries…

By Design With Calibre
2 MIN READ
SRAM physical verification – Why does it have to be so hard? (Hint: it doesn’t)

SRAM physical verification – Why does it have to be so hard? (Hint: it doesn’t)

December 19, 2017

By James Paris and Elven Huang – Mentor, A Siemens Business Checking SRAM IP placements can be tricky, even for…

By Design With Calibre
3 MIN READ