Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Where today meets tomorrow…

September 25, 2019

On September 4, 2019, Siemens PLM Software officially became Siemens Digital Industries Software. As the rate of innovation increases, and…

By Design With Calibre

2 MIN READ

Want a better, faster way to write reliability rules and checks? Try an XML constraint file!

August 30, 2019

By Dina Medhat – Mentor, A Siemens Business XML constraint files are the better, faster way to define Calibre PERC…

By Design With Calibre

2 MIN READ

SoC integration issues? Now you can find them earlier, and fix them faster

August 13, 2019

By Nermeen Hossam and John Ferguson – Mentor, A Siemens Business Our Calibre Recon tool helps SoC teams quickly find…

By Design With Calibre

2 MIN READ

That cloud looks like…a successful IC tapeout!

August 5, 2019

By Omar El-Sewefy – Mentor, A Siemens Business Running Calibre software in the cloud can help companies quickly adjust resource…

By Design With Calibre

2 MIN READ

Inductance parasitics: the enemy of analog/RF performance and reliability

July 18, 2019

By Hossam Sarhan – Mentor, A Siemens Business Ignoring interconnect inductance extraction in analog and RC designs can be a…

By Design With Calibre

2 MIN READ

Samsung and Mentor getting headlines with innovative fast LFD using machine learning

July 11, 2019

By Shelly Stalnaker – Mentor, A Siemens Business Tom Dillinger, editor at SemiWiki, recently attended the Samsung Foundry technology forum…

By Design With Calibre

3 MIN READ

Optimize design databases by deleting duplicate data

July 9, 2019

By James Paris – Mentor, A Siemens Business Are you suffering from data inefficiency? Learn how you can remove data…

By Design With Calibre

2 MIN READ

Automated full-chip ESD protection verification is here!

June 21, 2019

By Frank Feng – Mentor, A Siemens Business Full-chip ESD verification can be challenging, especially at advanced nodes. Adopting logic-driven,…

By Design With Calibre

2 MIN READ

Stronger, better, earlier latch-up protection? Yes, please!

June 14, 2019

By Flint Yoder – Mentor, A Siemens Business Tight schedules? Worried about product reliability? Now you can find and eliminate…

By Design With Calibre

2 MIN READ