By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm…
By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.
By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…
By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…
By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to comply with voltage-aware DRC spacing…
By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures…
By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…
