By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses that create high-voltage and multiple…
By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…
Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…
By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm…
By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.
By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…
By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…
