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Sometimes you just want less – Splitting IC layouts saves time and resources

Sometimes you just want less – Splitting IC layouts saves time and resources

April 16, 2019

By Dennis Joseph – Mentor, A Siemens Business One slice instead of the whole pizza. One single 1¼“ nail, not…

By Design With Calibre
2 MIN READ
Packaging custom checks standardizes and simplifies reliability verification

Packaging custom checks standardizes and simplifies reliability verification

April 10, 2019

By Hossam Sarhan, Mentor – A Siemens Business Using a packaged checks flow lets designers quickly select, configure and run…

By Design With Calibre
2 MIN READ
The power of innovation: Letting patterns create themselves with self-aligned multi-patterning

The power of innovation: Letting patterns create themselves with self-aligned multi-patterning

April 5, 2019

By David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy – Mentor, A Siemens Business Given the alignment control issues in traditional litho-etch…

By Design With Calibre
2 MIN READ
3D InCites community awards Mentor, a Siemens Business “EDA Provider of the Year” for 3rd consecutive year!

3D InCites community awards Mentor, a Siemens Business “EDA Provider of the Year” for 3rd consecutive year!

March 13, 2019

Every year, 3D InCites, an online media resource dedicated to all things 3D in the semiconductor industry, recognizes company and…

By Design With Calibre
2 MIN READ
Context-aware verification checks enhance checking and debugging capabilities

Context-aware verification checks enhance checking and debugging capabilities

February 15, 2019

By Sherif Hany – Mentor, A Siemens Business Automated context-aware verification helps designers ensure the performance and reliability of complex…

By Design With Calibre
2 MIN READ
Silicon photonics design and verification joining the mainstream

Silicon photonics design and verification joining the mainstream

February 5, 2019

By John Ferguson – Mentor, A Siemens Business Silicon photonics offers up the promise of blazing fast data transmission and…

By Design With Calibre
2 MIN READ
Lane ends—full-chip merge ahead

Lane ends—full-chip merge ahead

January 21, 2019

By James Paris – Mentor, A Siemens Business Fast layout merging during continuous build flows makes it easier to solve…

By Design With Calibre
2 MIN READ
Simplify your life with Calibre RVE filters!

Simplify your life with Calibre RVE filters!

January 14, 2019

Sometimes there are simply too many choices in life. Who needs 35 flavors of juice, or 20 different hammers? Having…

By Design With Calibre
< 1 MIN READ
Vroom! Vroom! Getting to the tapeout finish line faster…

Vroom! Vroom! Getting to the tapeout finish line faster…

January 3, 2019

By Srinivas Velivala – Mentor, A Siemens Business The Calibre RealTime Digital interface helped Qualcomm spend less time fixing DRC…

By Design With Calibre
2 MIN READ