How to classify unique DRC results in Calibre RVE

Activating the Shape Class property in your Calibre RVE tool setup allows you to classify…

How To Navigate Through OPC Simulation Results in Calibre WorkBench

Learn how to quickly and easily scan multiple layers of Calibre OPC simulation results in…

Fill/Cut Self-Aligned Double-Patterning

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke How the SID-SADP process affects…

Creating An Accurate FEOL CMP Model

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Context-Aware Latch-up Checking

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help…

Efficient Parasitic Extraction Techniques for Full-Chip Verification

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC…

How Do I ECO a Multi-Patterned Design?

By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multiĀ­patterned designs can be…

Colorless vs. Colored Double-Patterning Design Flows

By David Abercrombie, Mentor Graphics How do you know which double patterning flow to use?…