My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…
Psst! I’ll let you in on some news… While DVCon calls the free portion of the conference “Exhibits Only,” let…
Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable”…
MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…
It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added…
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from…
You don’t need a graphic like the one below to know that multi-core SoC designs are here to stay. This one…
Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs that present the highlights from…
