Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of…
A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is…
The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the press; though I…
A new style takes center stage It was Fashion Week in Portland, Oregon in early October. And while the thought…
At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug:…
A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According…
Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification…
Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the…
“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…
