It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…
“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…
Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…
Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…
Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase…
System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…
Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…
The standards developing organizations defining and updating front-end EDA standards will be at DAC in force. And from the looks…
