OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards” The EDA industry has seen changes to the international standards…
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group…
Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…
It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…
“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…
Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…
Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…
