UVM: Some Thoughts Before DVCon

UVM: Some Thoughts Before DVCon

It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…

UVM™ at DVCon 2012

UVM™ at DVCon 2012

“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

VHS or Betamax?

VHS or Betamax?

Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…

Verification Issues Take Center Stage

Verification Issues Take Center Stage

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…

Going from “Standards Development” to “Standards Practice”

Going from “Standards Development” to “Standards Practice”

Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase…

Accellera & OSCI Unite

Accellera & OSCI Unite

System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…

Part 8: The 2010 Wilson Research Group Functional Verification Study

Part 8: The 2010 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…

Getting Your Standards Update @ DAC 2011

Getting Your Standards Update @ DAC 2011

The standards developing organizations defining and updating front-end EDA standards will be at DAC in force.  And from the looks…