Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over…
When I was at DAC this year, I had a few folks come up to me at our Verification Academy…
DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…
Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops…
From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…
The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global. Accellera System Initiative has…
As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately,…
Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …
Verification engineers put lots of effort into writing and tuning constraints for random stimulus. It’s critical that the constraints correctly…
