Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends…
Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified…
Hi Everyone, Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition…
Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard,…
Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of…
A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is…
Power Aware Verification Course Modules Released I guess I could continue the puns on the low-power theme as a few…
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional…
We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check…
