Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…
FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective…
This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…
This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
2014 was an exciting year for formal verification to say the least, and below I call out a sampling of…
Just in time for Christmas and other year-end holidays, I am pleased to announce that the latest issue of Verification…
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…
Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design,…
