Portable Stimulus at DVCon

It’s amazing how quickly a year goes by. DVCon 2014 seems like it was just a few months ago, and here we are rolling up on DVCon 2015. As my colleague Dennis Brophy blogged earlier, it was just a year ago that Mentor Graphics proposed that Accellera launch a Proposed Working Group (PWG) to explore whether sufficient need and interest existed in the industry to standardize a portable stimulus specification. After nearly a year of requirements gathering and discussion between the participants of the Portable Stimulus PWG, the PWG announced that it had concluded there was sufficient interest and need to justify an official standards body.

When portable stimulus is discussed, it is often in the context of SoC-level verication – both because of how critical SoC- and System-level verification is today, and because of the stresses an SoC-level environment places on a portable stimulus solution. SoC-level verification must be done in simulation, emulation, and silicon, and is typically driven via the embedded processors in the design – in other words, using the design to verify itself. In an SoC-level environment, Portable Stimulus introduces a degree of stimulus-generation automation not possible using directed tests, while enabling the generated stimulus to be portable across engines and tailored to the performance characteristics of those engines.

While SoC-level verification may illustrate an extreme example of the requirements for portable stimulus, there are many other cases where portable stimulus is extremely valuable. One of these cases is illustrated by a paper co-authored by Boris Hristov from Ciena , and my colleague, Mike Andrews. Portable Stimulus Models for C/SystemC, UVM and Emulation discusses how portable stimulus can be applied to verify a C/SystemC design that will be targeted at High-Level Synthesis (HLS). Then, reuse the same stimulus model to verify the RTL output of the High-Level Synthesis tool in a UVM environment in simulation and emulation. While a very different target than SoC-level verification, the benefits of applying Portable Stimulus are much the same – consistent stimulus across languages and engines, and a high degree of automation.

So, if you’re attending DVCon be sure to check out the presentation for Portable Stimulus Models for C/SystemC, UVM and Emulation. It’s on Tuesday afternoon in the Multi-Language session: http://dvcon.org/content/event-details?id=180-7

Come find me in the Mentor Graphics booth (booth 801), and I’ll be happy to discuss verification in general and Portable Stimulus, specifically, in more depth with you.


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