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DVCon India: A Smashing Hit!

DVCon India: A Smashing Hit!

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…

Portable and Productive Test Creation with Graph-Based Stimulus

Portable and Productive Test Creation with Graph-Based Stimulus

Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops…

Supporting A Season of Learning

Supporting A Season of Learning

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

DVCon Goes Global!

DVCon Goes Global!

The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global.  Accellera System Initiative has…

Better Late Than Never: Magical Verification Horizons DAC Edition

Better Late Than Never: Magical Verification Horizons DAC Edition

As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately,…

Accellera Approves UVM 1.2

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …

Getting More Value from your Stimulus Constraints

Getting More Value from your Stimulus Constraints

Verification engineers put lots of effort into writing and tuning constraints for random stimulus. It’s critical that the constraints correctly…

The FPGA Verification Window Is Open

The FPGA Verification Window Is Open

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…

UVM DVCon 2014 Tutorial Video Online

UVM DVCon 2014 Tutorial Video Online

DVCon 2014 Conference Proceedings Published With record attendance announced for DVCon 2014, one might wonder if there is really a…