Thought Leadership


By Tom Fitzpatrick

As I’m sure I’ve mentioned before, DVCon (in the US – I haven’t made it to any of the new, international events yet) is one of my favorite weeks of the year. In addition to seeing friends and colleagues, I really enjoy seeing how the industry has progressed from year to year. As one of the early (and still enthusiastic) proponents of UVM, I was especially interested to see all the UVM-related activity at this year’s conference.

The UVM emphasis started first thing Monday morning with the tutorial “Preparing for IEEE UVM Plus: UVM Tips and Tricks,” which by my unofficial tally was the most well-attended tutorial on Monday. Judging by the audience’s attentiveness, it was apparent that they found the “Tips and Tricks” discussion, which was divided into compile-time and run-time categories, to be very helpful, although many of them are already included in the online UVM Cookbook on Verification Academy. In addition, there were three separate “UVM Applications” sessions, each of which was the most popular session in its timeslot, and 9 posters on UVM.

One poster in particular caught my eye, “Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse,” (viewable here) by my Mentor Graphics colleague Bob Oden and Mike Baird of Willamette HDL. Bob is the creator of our new UVM Framework reuse environment (more about that in a future post) and, besides being one of the leading UVM and SystemVerilog trainers out there, Mike holds the distinction of being the guy who taught me Verilog way back in the dark ages. These guys really know their stuff, and the paper lays out a straightforward approach to organizing, grouping, and packaging the different parts of your UVM component library to maximize their reuse from project to project. It also shows you how to architect your components and environments to make them self-contained and configurable so you’ll be able to use them in whatever context you need to.

Given the remarkable and still-growing popularity of UVM, I’m going to take some time over the next few weeks and months to highlight some of the key points of effective UVM usage here on Verification Horizons. As you know, there’s a wealth of UVM-related information on Verification Academy, but I think it might help to point out some of the more important features. Stay tuned!

By the way, you can see all of the papers and posters written by Mentor Graphics authors here. Enjoy!

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This article first appeared on the Siemens Digital Industries Software blog at