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Still waiting… It’s Friday afternoon, and I don’t have my RTL

Still waiting… It’s Friday afternoon, and I don’t have my RTL

Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on…

FPGA Prototyping is coming home

FPGA Prototyping is coming home

Does anybody remember Daisy PLDMaster? Okay, Methuselah, you can put your hand down now. Some time back in the late…

No to Know VIP – Validated!

No to Know VIP – Validated!

We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how…

DVCon USA 2016: Heralding Formal’s New Wave

DVCon USA 2016: Heralding Formal’s New Wave

If you were wondering whether formal verification is becoming a cornerstone of mainstream verification flows, several events at the recent…

DVCon US: UVM Is BIG

DVCon US: UVM Is BIG

As I’m sure I’ve mentioned before, DVCon (in the US – I haven’t made it to any of the new,…

Introducing the Verification Academy Patterns Library!

Introducing the Verification Academy Patterns Library!

If you have been involved in either software or advanced verification for any length of time, then you probably have…

Verification Horizons Newsletter DVCon Edition Available

Verification Horizons Newsletter DVCon Edition Available

Just wanted to take a minute from DVCon to let you know that the latest super-sized Verification Horizons is now…

Portable Stimulus Applications at DVCon 2016

Portable Stimulus Applications at DVCon 2016

  It’s that time of the year again – time for verification engineers and vendors alike to show off the…

Debug Data API In Action

Debug Data API In Action

First Debut of Working API at DVCon U.S. 2016 The Debug Data API is set to make its first public…