There are intrinsic limitations in the current approach for estimating dynamic power consumption. Briefly, the approach consists of a file-based…
Do you have a really tough verification problem – one that takes seemingly forever for a testbench simulation to solve…
Learn more about DDA at DAC At DAC – Mentor Graphics and Cadence Design Systems are coming together to usher…
I am please to announce that, beginning today, the Accellera Portable Stimulus Working Group (PSWG) is accepting technology contributions to…
FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…
This year we are trying something new at the Verification Academy booth during next week’s 2015 Design Automation Conference. We’ve…
Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…
In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…
FPGA Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…
