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Part 9: The 2016 Wilson Research Group Functional Verification Study

Part 9: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

Debugging My UVM Factory and UVM Config

Debugging My UVM Factory and UVM Config

UVM and Better Debug – The UVM Factory and Config conspire against me   Sitting in my chair pulling out…

Part 8: The 2016 Wilson Research Group Functional Verification Study

Part 8: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Resource Trends This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group…

Part 7: The 2016 Wilson Research Group Functional Verification Study

Part 7: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Design Trends This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group…

Taming the Verification Debug Monster

Taming the Verification Debug Monster

Join us for the Verification Academy Live Seminar on Enterprise Debug & Analysis Your designs are larger and more complex…

Part 6: The 2016 Wilson Research Group Functional Verification Study

Part 6: The 2016 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

Part 5: The 2016 Wilson Research Group Functional Verification Study

Part 5: The 2016 Wilson Research Group Functional Verification Study

FPGA Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

Part 4: The 2016 Wilson Research Group Functional Verification Study

Part 4: The 2016 Wilson Research Group Functional Verification Study

FPGA Verification Effectiveness Trends This blog is a continuation of a series of blogs related to the 2016 Wilson Research…

How Mature is your Design/Verification Organization?

How Mature is your Design/Verification Organization?

We had a good office discussion recently about various chip design/verification groups that my colleagues and I have been a…