Our special year-end issue of the Verification Horizons Newsletter (for which this blog is named, by the way) is now available! The Editor’s Note, written by “yours truly,” gives an overview of each of the articles, as well as sharing about my son’s unique ability to fix a problem with his phone. But I wanted to share with you a couple of articles in particular.
For those of you working on safety-critical designs in particular, the featured article, EDA Support for Functional Safety — How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety, from our friends at IROC Technologies, will help you to build and optimize a fault model for your design to define the set of faults to be injected during verification. Even if you’re not following the ISO26262 Automotive Safety Standard, the techniques will help you gain a better understanding of the things that might go wrong in your design and how to protect against them.
In Step-by-Step Tutorial for Connecting Questa VIP into the Processor Verification Flow, our friends at Codasip Ltd. show how they’ve taken advantage of Mentor’s new Questa Verification IP (QVIP) Configurator tool make it easy to include QVIP components in their auto-generated processor verification environments. The Configurator is a great enhancement to the usability of our highly-configurable QVIP library and this article highlights the advantages to be found, whether you’re using Codasip’s automation flow or have your own QVIP-based verification environment.
The rest of the articles come from my colleagues at Mentor and are not to be missed:
- PA GLS: Power Aware Gate-Level Simulation
- Reset Verification in SoC Designs
- Debugging Inconclusive Assertions and a Case Study
- Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
I hope you all have a Merry Christmas and a happy and healthy New Year.