Latest posts

Accelerate Closure of Reset Path and Reset Domain Crossing Issues in Digital Designs

In today’s large, complex designs, multiple asynchronous resets have become the norm. The increase in reset domains is driven by…

Join us at Accellera’s DAC Luncheon to discuss PSS

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

Learn About the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle…

Mark your calendar for the 2024 DAC-Chips to Systems Conference

Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss!…

Navigating Reset Domain Crossings to Safety in Complex SoCs

As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic…

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

In Memoriam: Chris Spear

Our friend and colleague Chris Spear passed away suddenly. He was a long-time veteran of our industry and was known…

SystemVerilog

Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…

DVCon 2024 – Verify Real Number Models

Solving Puzzle Do you like to solve puzzles? I do, and I think every engineer does. Since we are solving…