Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage
Join Siemens EDA at the Future of Memory and Storage Conference, August 5–7, 2025, in Santa Clara, CA
Siemens EDA is proud to be a featured participant at the Future of Memory and Storage (FMS) 2025 conference, taking place at the Santa Clara Convention Center. As a leader in verification IP and system-level solutions, Siemens EDA will showcase cutting-edge innovations across CXL, UCIe, NVMe, and AI interconnect technologies.
Visit us at Booth #1140 to explore how our solutions accelerate time-to-market, enhance interoperability, and ensure robust system-level verification for next-generation memory and storage architectures.
Don’t Miss These Siemens EDA Presentations
- Tuesday, August 5
🕗 8:30–9:30 AM | Ballroom C
CXL Security Stack Verification and its Challenges
Presented by PJ Wang (on behalf of Richa Gupta)
Explore the full CXL security stack—from SPDM to IDE and TSP—and the verification strategies needed to secure data against physical attacks and unauthorized access.
- Wednesday, August 6
🕘 8:30–9:35 AM | Ballroom B
Revolutionizing Memory for AI/ML’s Future: MRDIMM
Presented by Pankaj Goel
Discover how MRDIMM delivers higher bandwidth, lower latency, and energy efficiency—key enablers for AI/ML workloads.
🕙 9:45–10:50 AM | Ballroom G
Software Aware Verification IP for CXL, NVMe, UCIe
Presented by Luis E. Rodriguez
Learn how Siemens’ platform bridges firmware, software, and hardware teams using open-source tools and SystemC for early system-level validation.
- Thursday, August 7
🕘 9:45–10:50 AM | Ballroom C
Pre-Migration Verification for NVMe SSDs: Ensuring Seamless Live Migration
Presented by Prashant Dixit
Gain insights into verifying NVMe live migration with reusable APIs, UVM features, and compliance test suites.
🕚 11:00 AM–12:00 PM | Ballroom E
Accelerating GFD RTL Verification: A Lightweight Host-to-GFD Framework
Presented by Wade Chen
See how Siemens’ lightweight framework simplifies GFD verification by bypassing full-fabric simulation.
🕛 12:10–1:15 PM | Ballroom D
Navigating the Chiplet Revolution
Mastering UCIe 2.0: Overcoming Fabric Management Hurdles for Chiplet Integration
Presented by Prashant Dixit & Ujjwai Negi
Learn how to manage complex SiP topologies and ensure protocol interoperability using UVM and reusable test environments.
Versatile Verification Framework for Multi-Protocol UCIe Design
Presented by Himani Kaushik
Discover a flexible adapter architecture that integrates diverse protocols over UCIe for streamlined system-level verification.
UCIe Chiplet Ecosystem: Interoperable Testbench for Multi-Vendor IP Integration
Presented by Prashant Dixit
Explore a simulation-based interoperability program that accelerates UCIe adoption through early collaboration.
🕐 1:25–2:30 PM | Ballroom B
CXL Verification: A Comprehensive Guide
A Comprehensive Verification Guide for Extended Meta Data
Presented by PJ Wang
Understand how to verify CXL 3.1’s Extended Meta Data with protocol checkers and error injection.
Enhancing Security in CXL: IDE and TSP Verification
Presented by PJ Wang & Wade Chen (on behalf of Heetashi Arora)
Dive into verification of CXL IDE and TSPs, including coherence, encryption, and access control scenarios.
🕐 1:25–2:30 PM | Ballroom C
Evolving UALink and UEC as the Gold Standard for Accelerator Connectivity in AI
Presented by Pankaj Goel
Learn how UALink and UEC deliver scalable, low-latency interconnects for AI workloads using existing PHY infrastructure.
We’re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025. Whether you’re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies. Let’s explore how Siemens EDA can help you accelerate innovation, ensure interoperability, and build the future of memory and storage—together.
