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UALink over UCIe 3.0: Maximizing Performance for Chiplet-based Designs

October 1, 2026

This blog is about how UALink and UCIe 3.0 come together to make chiplet‑based accelerator systems scale efficiently. It explains,…

By Mundru Sriram Bhaskar Teja
5 MIN READ
Image with chips and text that reads "The next chapter for PCIe: Chiplet integration with UCIe"

The next chapter for PCIe: Chiplet integration with UCIe

September 25, 2026

From processors and accelerators to storage, networking, and memory subsystems, PCI Express (PCIe) has been the backbone of modern compute…

By Kartik Sahajpal and Prashant Dixit
4 MIN READ

Pushing boundaries: Smarter verification for UCIe multi-die systems

September 18, 2025

The semiconductor industry is at a turning point. As demand for higher performance and energy efficiency continues to grow, chipmakers…

By Ujjwal Negi
4 MIN READ

Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage

July 31, 2025

We’re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025. Whether you’re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies.

By Dennis Brophy
2 MIN READ
Circuit board with chip and binary data depicting interface Protocol Verification

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

August 6, 2024

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…

By Gordon Allan
3 MIN READ

Verification Challenges and Solutions for Multi-Die Systems (UCIe) 

July 29, 2024

Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…

By Vivek Kaliki
2 MIN READ