By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…
Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…
When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make or break tapeout plans. Working…
By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential component of many of the…
Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…
By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…
