How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make or break tapeout plans. Working…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential component of many of the…

Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

Efficient Parasitic Extraction Techniques for Full-Chip Verification

Efficient Parasitic Extraction Techniques for Full-Chip Verification

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…

Collaborative SoC Verification

Collaborative SoC Verification

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…