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Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

By Design With Calibre
5 MIN READ
Efficient Parasitic Extraction Techniques for Full-Chip Verification

Efficient Parasitic Extraction Techniques for Full-Chip Verification

May 26, 2016

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…

By Design With Calibre
6 MIN READ
Collaborative SoC Verification

Collaborative SoC Verification

April 11, 2016

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…

By Design With Calibre
4 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ
Automated Chip Polishing Can Make Your Design Shine

Automated Chip Polishing Can Make Your Design Shine

July 14, 2015

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and reduces yield variability over its…

By Design With Calibre
4 MIN READ